Digital workflow for the process chain for semiconductor epitaxial layers with large bandgap for power electronics.

The deposition of functional layers on wafers is a central step in the manufacturing of semiconductor
devices. The processing of the devices and the extraction of the characteristic data represent the next
essential step in the process chain. In this project, an ontology will be created for the area from wafer to
device, which maps the process chain in this area, with a focus on epitaxy and subsequent process
technology. Since the development is intended for an industrial environment, "Privacy Preserving ML" will
also be tested. The algorithms will be developed on the GaN/Si system, as there is a large amount of data
available and many physical fundamentals are better known. Here, digitization will be used for further
(automatic) optimization of production processes in epitaxy, including the consideration of data from device
manufacturing ("Digital Feedback Loop"). In addition to vertical transistors as target devices, high-voltage
diode structures will be used as highly sensitive measurement structures. Thus, the progress in
semiconductor growth can be explored and practically demonstrated and fed back using the digital twin.
The developed models will be used to test the more innovative and less developed material system Ga2O3.
A generic further development of this new method for application to other material systems already
established in the industry (GaAs, InP, SiC) with a much higher level of development is aimed for. The
transfer to new N-compound semiconductors, such as ScN, MnN, YAlN, or ScAlN, is also possible and
industrially relevant.